Field of the Invention
The present invention relates to read/write amplifiers for DRAM memories which are embodied with vertical transistors.
Dynamic Random Access Memories (DRAM memories) represent the most important type of memories for storing digital information. Each DRAM memory cell comprises a transistor for addressing the cell and a capacitance for storing a charge which represents the information stored in the memory cell.
The memory cells are connected in matrix-type arrangements. What is called a word line and a bit line lead to each memory cell, all the memory cells of a row being connected to the same word line or to two word lines which are respectively connected to every second cell and each of the rows of the matrix of memory cells being connected to one or two bit lines. Activation of a specific word line enables all the memory cells connected thereto to be read via their bit lines, written to or refreshed with regard to their information content. Refreshing is necessary in DRAM memory cells since the charge stored in the capacitance is lost over the course of time on account of leakage currents, especially in the case of integrated modules.
In order to read out the information contained in memory cells, or in order to refresh the information, what are called read/write circuits are used, which are respectively connected usually to two bit lines. The coupling to two bit lines enables a comparison of the charge differences and thus simplifies the assessment of a memory cell content.
FIG. 1 shows an example of such a read/write devicexe2x80x94known in the prior artxe2x80x94for reading DRAM memory cells. This circuit essentially comprises a multiplexer section A, an evaluation section B and a precharge/equalize section C. The heart of the circuit is formed by the evaluation section B with a flip-flop which comprises two transistor pairs having transistors of the same polarity, namely the nMOS transistors T1 and T2, and respectively the pMOS transistors T4 and T5. In the present example, the read/write amplifier is connected to two bit lines, the bit line BL and the reference bit line BBL. In this case, BBL is connected via the connection 10 to the gate of the transistor T1, while BL is connected via the connection 12 to the gate of the transistor T2. Furthermore, BBL is connected via the connection 11 to one of the source/drain regions of the transistor T2 and BL is connected via the connection 13 to a source/drain region of the transistor T1.
The other source/drain region of the two transistors is connected via the SAN connection 14 to the transistor T3, which can be switched via the connection 15 by means of the signal NSET via the signal line, or interconnect 17, in order to be able to be pulled to ground (GND). This is done via the ground line 18 and the connection 16, which is connected to the other source/drain region of the transistor T3. The second transistor pair, comprising the transistors T4 and T5, is connected up in the same way to the bit lines BL and BBL, but VDD rather than ground can be applied to the transistor T6. This circuit arrangement effects a segregation of the possible signal states to form unambiguous signal levels, which allows assessment of the cell content with regard to logic 1 or logic 0.
The multiplexer section A comprises the two transistors T7 for the bit line BL and T8 for the bit line BBL. In this case, the bit line BL is connected via the connection 34 to a source/drain region of the transistor T7, while the bit line BBL is connected via the connection 31 to the transistor T8. Via the MUX line 36, a multiplexer signal can be fed to the connections 33 and 30 of the transistors T7 and T8, with the result that the latter switch on. In the event of switch-on, the voltage present on BL, and respectively BBL, is forwarded via the connections 35 and 32.
Finally, the precharge/equalizer section C comprises the three transistors T9, T10 and T11. While BBL is connected via a connection 40 to a source/drain region of the transistor T10, BL is connected via the connection 42 to a source/drain region of the transistor T9. The respective other source/drain regions of the two transistors T9 and T10 are connected via the connection 44 to the VBLEQ signal line 46. The transistor T11 is simultaneously connected to both bit lines in its source/drain region via the connection 41 to BBL and via the connection 43 to BL. All three gate regions of the transistors T9, T10 and T11 are connected via the connection 45 to the EQ line 47. The circuit described here for a read/write circuit is to be regarded as by way of example. It is not intended to restrict the invention and can undergo numerous variations.
DRAM memory modules are subject to intense cost pressure. Today""s DRAM memories are realized practically exclusively as integrated semiconductors in which the arrangements of memory cells, word line including word line driving arrangement, bit line including the bit line driving arrangement, etc, are projected on an integrated circuit directly as structures of a silicon wafer. The main factor in the costs of fabricating integrated circuits is the size of the silicon surface used in each case. Therefore, under the existing cost pressure, there are great efforts to make the chip area for a specific number of memory cells, including their support logic, as small as possible. Continual miniaturization is practically permanently necessary for reasons of cost pressure. To that end, the inherent architecture of the DRAM memory cell is also permanently being optimized. Starting from the 1 Gbit generation, the architecture of such a DRAM memory cell enables an area consumption of less than 8 F2, where F represents the minimum feature size that can be produced lithographically or half a grid width of a bit line in a sequence of parallel bit lines. A consequence of this reduction of area is that for the bit line architecture there is a transition from a xe2x80x9cfoldedxe2x80x9d concept, in which typically two word lines which respectively address every second cell are routed beside one another, to what is called the xe2x80x9copenxe2x80x9d concept, in which just one word line is used, which can address each cell of a row. A comparison of the quantities of charge of two adjacent bit lines is at present impossible in this way. Therefore, a parallel reference bit line cannot be used as a reference. Instead, a reference bit line is routed to another cell array in order still to be able to carry out a comparison of the voltages of an addressed bit line and of a nonaddressed reference bit line. The omission of the second, parallel bit line reduces the available width for the read/write amplifier. As a consequence of DRAM memory cell miniaturization, with a conventional word-line and bit-line arrangement, the available space for the read/write amplifier decreases in width from hitherto 8 F to 4 F. In a further embodiment, two bit lines which lead to different cell arrays, for example cell arrays adjacent in strips, are arranged one above the other.
Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide a read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. Instead, it has been necessary to adapt the arrangement of the read/write circuits on the chip to the conditions of the reduced cell size. However, such arrangements once again increase the area requirement of the read/write circuits to be accommodated and thus adversely affect the overall costs of each individual DRAM memory module.
The invention is thus based on the object of providing a read/write circuit which can be inserted into the reduced grid with a width of just 4 F of modern DRAM memory modules.
This object is achieved by providing an integrated read/write circuit that includes at least one vertical transistor and/or by providing an integrated DRAM memory that includes a read/write circuit with at least one vertical transistor.
The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by xe2x80x9cvertical transistorsxe2x80x9d in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.
Accordingly, the invention is directed at an integrated read/write circuit for evaluating at least one bit line in a DRAM memory which is characterized in that at least one transistor used in the read/write circuit is a vertical transistor.
The read/write circuit can have, in a customary manner, at least two transistor pairs of different channel types for evaluation purposes, in which case the transistors used for the transistor pairs of the read/write circuit may be vertical transistors. Since the transistor pairs usually form the heart of a read/write circuit, this makes it possible to cover a sufficiently small space in order to be able to achieve the object according to the invention.
In order to enable a particularly space-saving arrangement of the vertical transistors within a transistor pair, it may furthermore be preferred for these to have a common source/drain region via which they can be supplied with the respectively necessary voltage (SAN, SAP inputs). Since in each case one of the source/drain regions of the transistors of each transistor pair are at a common potential, this solution is suitable for obtaining a further simplification of the silicon regions required on the chip.
Transistors are also used for connecting the voltages (VDD, GND) required for operation of the transistor pairs to the transistor pairs. According to the invention, these transistors may also be vertical transistors.
An even more extensive simplification of the circuit can be obtained by both the vertical transistors of an arbitrary transistor pair and the vertical transistor used for connecting the voltage for this transistor pair having a common source/drain region.
As shown in FIG. 1, the source/drain regions of the transistor pairs are linked to the associated switching transistors anyway, so that the installation of a common source/drain well is appropriate. The common source/drain region of the vertical transistors may be connected to a voltage source (VDD or GND) via a SET line, that is to say an NSET or a PSET line depending on the type of transistor.
In order to be able to achieve the space saving sought, it is preferred for the vertical transistors used for the transistor pairs to have a width in the transverse direction with respect to the at least one bit line such that it approximately corresponds to the grid width of the bit lines. In this case, the grid width of a bit line is the extent encompassed by the width of one bit line including the necessary distance from the next bit line. This makes it possible to ensure that the two transistors required for each transistor pair can be arranged beside one another, which, for example, simplifies the use of common source/drain regions.
Furthermore, the read/write circuit according to the invention preferably has a multiplexer circuit for switching the at least one bit line, the transistors used for the multiplexer circuit being vertical transistors. By realizing further assemblies of the read/write circuit with the aid of vertical transistors, it is possible to eliminate further bottlenecks in the layout. The multiplexer circuit can also expediently be designed in such a way that it fits into the predetermined grid.
To attain a further space saving, at least some of the vertical transistors for switching all the bit lines may have a common polysilicon gate region. In this case, xe2x80x9callxe2x80x9d the bit lines should be understood to mean all the bit lines which are assigned to a specific read/write circuit, but not all the bit lines which are actually present in the DRAM memory.
Furthermore, the common polysilicon gate region of the vertical transistors may preferably be connected to a multiplexer signal source in order to be able to switch the transistors via the gate regions.
Finally, the read/write circuit according to the invention may also have a precharge/equalize section, in which case the transistors used for the precharge/equalize circuit may be vertical transistors.
Consequently, it is possible for all three subcircuits of the overall read/write circuit according to the invention to be equipped with vertical transistors at least in parts. It is particularly preferred if the entire read/write circuit is equipped with vertical transistors in all its parts, in order to be able to comply with the predetermined narrow grid of modern DRAM memories.
Preferably, at least some of the vertical transistors of the precharge/equalize circuit have a common polysilicon gate region. Here, too, the basic principle manifested is once again that of projecting connectable regions of different transistors by means of common structures in the silicon in order to keep the overall structure simple and to reduce the spatial requirement.
The common polysilicon gate region of the vertical transistors of the precharge/equalize circuit is preferably connected to an equalize signal source (EQ).
Furthermore, the precharge/equalize circuit may have a transistor for each of the at least one bit line, which transistor is connected to a voltage source at a source/drain region, these source/drain regions of the transistors forming a common source/drain region.
In terms of their construction, the vertical transistors preferably have a projection on the substrate material, whose side walls act as a channel, a first source/drain region formed by a layer which is arranged on the projection and is made of material having an inverse doping with respect to the substrate, a second source/drain region formed by a layer which is arranged on the substrate beside the projection and is made of material having an inverse doping with respect to the substrate, and a gate region made of polysilicon. The gate region is arranged on the side walls of the projection and on the junction between the side walls of the projection and the second source/drain region. Furthermore, the polysilicon may form a polysilicon contact region in order to be able to make contact with the gate region.
This preferred arrangement of a vertical transistor makes it possible to achieve a major space saving in comparison with the use of conventional, horizontally arranged transistors. By way of example, the projection may be designed in such a way that, in the transistors of the transistor pairs, it has a width which allows it to be inserted into the width grid of the bit lines, i.e. a width which approximately corresponds to half a grid width of the bit line (since the interspaces must also be realized). In this case, therefore, it is possible to approach the lithographic minimum when forming structures. Other transistors may have a projection whose width approximately corresponds to the grid width of one bit line, with the result that they occupy the entire grid width up to the next bit line and fit into two grid widths. This may be preferred when there is no need to provide two adjacent transistors for each bit line or bit line group, rather just one transistor, but the latter possibly has to be controlled by two bit lines.
The read/write circuit according to the invention is, in particular, preferably characterized in that it is connected to two bit lines. An arrangement with two bit lines corresponds to the previous procedure in the design of read/write devices and simplifies the application of the transistor pairs, since the latter can be supplied by the two bit lines. The bit lines can lead to different memory sides of the DRAM memory. However, it may be preferred to have the two bit lines lead to one memory side. In this case, it is appropriate for the two bit lines to be arranged above the read/write circuit and one above the other with regard to the main plane of the DRAM memory. The bit lines can then be connected to the vertical transistors preferably via essentially vertical interconnects which reach from the bit lines down to the transistors.